1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to methods and apparatus for improved memory self-timing circuitry.
2. Description of the Related Art
Semiconductor memory cores are usually laid-out in array format, such that each individual core cell is coupled by a wordline and a pair of differential bitlines. To access data stored in a selected core cell, associated memory accessing circuitry is commonly designed around a memory core. For example, some of the key memory accessing circuitry typically includes addressing circuitry for selecting a core cell, wordline drivers for driving a selected wordline, and sense amplifiers for amplifying the signal read from the selected core cell.
For ease of understanding, FIG. 1 shows a block diagram of a memory circuit having a memory core 100 and associated access circuitry. As in conventional memory core designs, a plurality of core cells 102 are laid out in throughout the memory core 100. In this example, a control block circuit 110 is used to control access to selected memory core cells 102 through the use of wordline drivers 106 and sense amplifiers (SA) 104.
In this example, the control block circuit 110 is configured to produce a signal that triggers a selected wordline driver 106 upon a rising edge of the signal 116a. When the signal 116 experiences a falling edge (ie., at a time determined by a conventional self-timing architecture described below), the signal 116b will initiate the sensing of data through one of the selected sense amplifiers 104. As shown, the wordline drivers 106 are connected to each of the core cells 102 through the use of wordlines that interconnect each of the core cells 102 in a horizontal direction. In a like manner, the sense amplifiers 104 are connected to each of the core cells 102 in the vertical direction, through the use of differential bitlines.
In conventional memory circuitry, designers have used a self-timing architecture that enables a memory circuit to determine when the sense amplifiers 104 should commence sensing data from the core cells 102 in the memory core 100. Self-timing architectures are generally used to approximate a standard delay time (i.e., which is generally the worst case timing delay for a given core) which will be used when an access to any one of the core cells 102 is attempted. The self-timing architecture is generally needed because the actual delay time of a particular core cell 102 will generally be different depending on the location of the particular core cell 102. By way of example, a core cell 103 is located at the furthest location from a given wordline driver 106 and a given sense amplifier 104.
Therefore, an RC delay associated with the wordline that couples the wordline driver 106 to the core cell 103, and the RC delay associated with the bitlines that couple a sense amplifier 104 to the core cell 103, will have a combined RC delay that is larger than any other core cell 102 in the memory core 100. For example, the combined RC delay of the wordline and the bitlines that couple to a core cell 101, will be smaller than any other core cell that is laid out in the memory core 100. Therefore, the self-timing architecture which includes a model wordline driver 106', core cells 102', a model core cell 103', a model wordline 112a, model bitlines 112b, sense amplifier 104', and a self-timing return path 114 serves to establish the aforementioned standard delay time.
Accordingly, the self-timing architecture is well suited to estimate when enough bitline differential has been achieved (i.e., due to the worst case model core cell 103') to correctly perform a sense amplification to read the data of a given core cell 102 in the memory core 100. In operation, the control block circuitry will initiate a select signal 116a to the model wordline driver 106' to access the model core cell 103'. When the model core cell 103' has been accessed, a signal is passed through the model bitlines 112b, through sense amplifier 104' and along the self-timing return path 114, that communicates to the control block circuit 110.
A particular problem with conventional self-timing architectures is that memory circuit will be ready to read data once the sense amplifier 104' has received the signal from the model core cell 103'. However, the additional self-timing return path 114 will necessarily add an additional RC delay to the RC delay of the model wordline 112a and the model bitline 112b. This additional RC delay introduced by the self-timing return path 114 will unfortunately slow down a memory accessing operation. As such, the control block circuit 110 will not initiate a ready-to-read signal 116b to a given sense amplifier 104 until the control block circuit 110 receives the signal from the self-timing return path 114. Consequently, in applications where high-speed memory accessing is required, the performance of the entire memory circuit will suffer due to the additional RC delay introduced by the self-timing return path 114.
In view of the foregoing, there is a need for self-timed memory circuitry that avoids the introduction of unnecessary RC delays when access to a worst-case model core cell is performed.